1. Field of the Invention
The present invention relates to a synchronization signal generation circuit for switching an internally-generated synchronization signal and a synchronization signal which is in synchronization with an externally-supplied vertical synchronization signal, and to an image display apparatus using such a synchronization signal generation circuit.
2. Description of the Related Art
In an image display apparatus using a liquid crystal panel or the like, in the case where images, characters, patterns, etc., are displayed based on an external composite video signal on a display screen in a superimposed fashion, the synchronization mode of the image display apparatus is switched between the internal synchronization mode where a vertical synchronization signal internally generated by a vertical synchronization signal generation circuit and a horizontal synchronization signal which is in synchronization with the internally-generated synchronization signal are output to a display section and the external synchronization mode where an externally-supplied vertical synchronization signal and a horizontal synchronization signal which is in synchronization with the externally-supplied synchronization signal are output to the display section. When the synchronization mode is switched, the signal level of the composite video signal which is output to the display section sharply changes at some points in its waveform, and accordingly, the vertical synchronization signal and the horizontal synchronization signal which are output to the display section have irregular frequencies. As a result, an image displayed on the display screen is temporarily disturbed.
As a means of addressing such a problem, a synchronization method which maintains the vertical synchronization signal and the horizontal synchronization signal which are output to the display section at regular frequencies is disclosed in Japanese Laid-Open Publication No. 6-178206 and Japanese Laid-Open Publication No. 7-177469.
FIG. 6 is a block diagram showing a circuit 6000 which uses an image display switching method disclosed in Japanese Laid-Open Publication No. 6-178206.
In the circuit 6000, a superimpose circuit 1 generates a superimpose signal based on an external composite video signal supplied from outside and outputs the generated external composite video signal to an analog switch (switching section) 5. The superimpose signal is a composite signal for displaying images, characters, patterns, etc., based on the external composite video signal on the display screen in a superimposed fashion.
Furthermore, the circuit 6000 has an inverter 7 for inverting the polarity of an internal synchronization signal, and an output of the inverter 7 is supplied to one of inverted input terminals of a NOR gate 8. The other inverted input terminal of the NOR gate 8 receives an output-off signal SOFF1. The NOR gate 8 logically synthesizes the signal output from the inverter 7 and the output-off signal SOFF1, and outputs the resultant synthesized signal to an internal composite video signal generation circuit 2.
The internal composite video signal generation circuit 2 generates, based on the signal from the NOR gate 8, a blueback signal which is a composite video signal for displaying images, characters, patterns, etc., on the display screen in a superimposed fashion. This blueback signal is input to an analog switch (switching section) 6.
Furthermore, the circuit 6000 has an inverter 3 for inverting the polarity of the externally-supplied synchronization switching signal S. A signal output from the inverter 3 is supplied to analog switches 5 and 6 and the inverter 4. The inverter 4 further inverts the polarity of the output signal from the inverter 3 and outputs a resultant signal to the analog switches 5 and 6. The analog switches 5 and 6 are controlled based on the signals output from the inverters 3 and 4 such that the states of the switches 5 and 6 differ from each other, i.e., such that when one of the switches 5 and 6 is open, the other is closed.
In the external synchronization mode, under the control of the signals output from the inverters 3 and 4, the analog switch 5 selects the superimpose signal supplied from the superimpose circuit 1 and outputs the selected superimpose signal as a composite video signal to the display section. The analog switch 6 is controlled based on the signals output from the inverters 3 and 4 such that the state of the analog switch 6 differs from that of the analog switch 5.
In the internal synchronization mode, the analog switch 6 selects the blueback signal supplied from the internal composite video signal generation circuit 2 and outputs the selected blueback signal as a composite video signal to the display section. When the analog switch 5 selects the superimpose signal, the analog switch 6 does not select the blueback signal.
FIG. 7 is a timing chart showing the signals described with reference to FIG. 6, i.e., a vertical synchronization signal included in the internal synchronization signal, a vertical synchronization signal included in the external composite video signal, the output-off signal SOFF1, the synchronization switching signal S, and a vertical synchronization signal included in the composite video signal output from the circuit 6000.
When the synchronization mode is switched from the internal synchronization mode to the external synchronization mode, the output-off signal SOFF1 rises to a high level before the synchronization switching signal S rises to a high level. With such an arrangement, the internal synchronization signal whose polarity has been inverted by the inverter 7 is supplied from the NOR gate 8 to the internal composite video signal generation circuit 2. Thus, during a period when the output-off signal SOFF1 is at a high level, the blueback signal is not output from the internal composite video signal generation circuit 2.
After the supply of the blueback signal from the internal composite video signal generation circuit 2 is continuously suspended (i.e., the blueback signal is “OFF”) for at least one field time or more, the synchronization switching signal S rises from a low level to a high level, whereby the synchronization mode is switched from the internal synchronization mode to the external synchronization mode. As a result, the analog switch 6 is turned off whereas the analog switch 5 is turned on. Thus, the superimpose signal generated by the superimpose signal circuit 1 is output as the composite video signal to the display section. Thus, the switching from the internal synchronization mode to the external synchronization mode is achieved by providing an OFF period of one field time or more between the internal composite video signal and the external composite video signal. With such an arrangement, the vertical synchronization signal included in the composite video signal which is output to the display section is prevented from having irregular frequencies.
FIG. 8 is a block diagram showing a frame pulse generation circuit 8000 in a record and reproduction apparatus disclosed in Japanese Laid-Open Publication No. 7-177469. A frame pulse is generated based on a vertical synchronization signal, and the vertical synchronization signal is generated based on the frame pulse. Thus, the frame pulse and the vertical synchronization signal are in synchronization with each other. A synchronization method in the frame pulse generation circuit 8000 is described as a method for synchronizing a vertical synchronization signal and a horizontal synchronization signal.
The frame pulse generation circuit shown in FIG. 8 includes a frame length determination section 11, an internal vertical synchronization signal generation section 17, a window pulse generation section 22, an output control section 23, and a timing control section 24. The frame length determination section 11 includes: a frame length detection circuit 12 for detecting a frequency of a frame pulse which is input to the frame length determination section 11 based on an externally provided vertical synchronization signal (i.e., for detecting the length of one frame length); and three comparators 13, 14, and 15 for determining the length of one frame of the frame pulse detected by the frame length detection circuit 12.
When one frame of the frame pulse detected by the frame length detection circuit 12 is longer than one frame of a frame pulse having a standard frequency by 1% or more of the one frame of the standard frequency frame pulse, the comparator 13 outputs a high level signal. When one frame of the frame pulse detected by the frame length detection circuit 12 is shorter than one frame of the frame pulse having the standard frequency by 1% or more of the one frame of the standard frequency frame pulse, the comparator 14 outputs a high level signal. When the difference of one frame of the frame pulse detected by the frame length detection circuit 12 and one frame of the frame pulse having the standard frequency is within a±1% range, the comparator 15 outputs a high level signal.
The output of the comparator 13 is supplied to a plus counter 18 of the internal vertical synchronization signal generation section 17 and to a previous frame state detection section 16. A signal output from the plus counter 18 is supplied to a frame pulse generation section 20 which generates a frame pulse having a frequency that is 1% or more higher than that of the standard frequency frame pulse.
The output of the comparator 14 is supplied to a minus counter 19 of the internal vertical synchronization signal generation section 17 and to the previous frame state detection section 16. A signal output from the minus counter 19 is supplied to a frame pulse generation section 21 which generates a frame pulse having a frequency that is 1% or less lower than that of the standard frequency frame pulse.
A switch 27 selects one of an output signal from the frame pulse generation section 20 and an output signal from the frame pulse generation section 21. The switch 27 is switched by the output control section 23 which is controlled by the previous frame state detection section 16. The output signal of the frame pulse generation section 20 or 21 is supplied to the timing control section 24 and to a switch terminal 28a of the switch 28 which is controlled by the timing control section 24. The timing control section 24 receives an output of the window pulse generation section 22 and the output of the comparator 15.
The output of the comparator 15 is supplied to a switch 25 provided between the input terminal 10 and the counters 18 and 19, to a switch 26 provided between the input terminal 10 and a switch terminal 28b of the switch 28, and to the timing control section 24.
An operation of the frame pulse generation circuit 8000 having the above structure is described below.
The input terminal 10 receives a frame pulse generated based on an externally-supplied vertical synchronization signal, and the generated frame pulse is supplied to the frame length detection circuit 12. The frame length detection circuit 12 detects rising edges of the frame pulse, thereby detecting the length of one frame of the frame pulse. When the difference in length between the detected one frame and one frame of the frame pulse having the standard frequency is within a ±1% range, the comparator 15 outputs a high level signal, whereby the switches 25 and 26 are turned on. As a result, the counters 18 and 19 of the internal vertical synchronization signal generation section 17 are reset in synchronization with a rising edge of the frame pulse. On the other hand, a frame pulse input through the input terminal 10 is supplied to the switch terminal 28b of the switch 28. The timing control section 24 controls the switch 28 based on the output signal from the comparator 15 such that a common terminal 28c of the switch 28 is connected to the switch terminal 28b. As a result, the frame pulse input through the input terminal 10 is supplied as it is to an output terminal 30. This state is in the external synchronization mode.
Alternatively, when the one frame detected by the frame length detection circuit 12 is longer or shorter than one frame of a frame pulse having a standard frequency by 1% or more of the one frame of the standard frequency frame pulse, the counter 18 or 19 operates based on the output signal from the comparator 13 or 14, whereby the output signal from the counter 18 is supplied to the frame pulse generation circuit 20 or the output signal from the counter 19 is supplied to the frame pulse generation circuit 21. As a result, a frame pulse is generated. In the meantime, based on the output signal from the comparator 13 or 14, an output signal from the previous frame state detection section 16 is supplied to the output control section 23, which in turn controls the switch 27 such that the common terminal 27c is connected to one of the switch terminals 27a and 27b. In addition to the switching of the switch 27, the timing control section 24 controls the switch 28 such that the common terminal 28c is connected to the switch terminal 28a, whereby the switch terminal 27a or 27b is connected to the common terminal 28c of the switch 28.
Thus, when the difference in length between the detected one frame and one frame of the frame pulse having the standard frequency exceeds a ±1% range, a frame pulse generated by the frame pulse generation section 20 or 21 is output from the output terminal 30. This state is in the internal synchronization mode.
When the synchronization mode is switched from the internal synchronization mode to the external synchronization mode, the window pulse generation section 22 is used to generate window pulses based on a frame pulse which is generated based on an externally-supplied vertical synchronization signal. Furthermore, even when the difference in length between the detected one frame of an externally-supplied frame pulse and one frame of the frame pulse having the standard frequency is within a ±1% range, the synchronization mode is not switched from the internal synchronization mode to the external synchronization mode until a frame pulse is generated by the internal vertical synchronization signal generation section 17 within an active area of the window pulse.
FIG. 9 is a timing chart for the signal output from the terminal 30 in the frame pulse generation circuit 8000 of FIG. 8 when the synchronization mode is switched from the internal synchronization mode to the external synchronization mode. In the case where window pulses are generated by the window pulse generation section 22 based on a frame pulse which is generated based on an externally-supplied vertical synchronization signal, the synchronization mode is not switched from the internal synchronization mode to the external synchronization mode until a pulse of an internal synchronization signal is generated within an active area of the window pulse. Thus, a frame pulse to be output (signal output from the terminal 30) can be kept at a regular frequency. Therefore, even when the difference in length between one frame of an externally-supplied vertical synchronization signal and one frame of the frame pulse having the standard frequency is within a ±1% range, the synchronization mode is not immediately switched from the internal synchronization mode to the external synchronization mode. As a result, the vertical synchronization signal to be output from the terminal 30 can be kept at a regular frequency.
In an image switching method using the circuit 6000 shown in FIG. 6, when a vertical synchronization signal included in an external composite video signal is input to the circuit 6000 at an irregular timing, the circuit 6000 outputs a vertical synchronization signal which is in synchronization with the vertical synchronization signal included in the external composite video signal which is input at an irregular timing. Furthermore, in the case where the display section to which the output vertical synchronization signal is supplied is a liquid crystal display device, if the OFF period of the blueback signal output from the internal composite video signal generation circuit 2 is equal to or longer than the time for discharging potential which is applied to a liquid crystal in the liquid crystal display device, display on the screen results in an abnormal state.
In the frame pulse generation circuit 8000 of the record and reproduction apparatus shown in FIG. 8, it is necessary to continuously supply a vertical synchronization signal from outside. Furthermore, information such as video data supplied from the outside, or the like, cannot be used until the synchronization mode is switched from the internal synchronization mode to the external synchronization mode. Thus, during such a period, a video image cannot be displayed. Furthermore, in a system to which a synchronization signal is supplied from outside in an irregular fashion (for example, a system including an image display apparatus where in a normal operation, a video image adjusted to the timing of a synchronization signal supplied from an external device (host device) is displayed while it is retained in (written in and read from) a frame memory inside the image display apparatus, and when the supply of the synchronization signal is stopped, writing in the frame memory is stopped, and a video signal retained in the frame memory is continuously read in the internal synchronization mode), when all or a portion of an image displayed on the display screen is replaced, the external apparatus only supplies the synchronization signal corresponding to the number of times that the display screen is replaced. Thus, the supply of the synchronization signal from outside may be stopped until a pulse of an internal synchronization signal is generated within an active area of the window pulse. In such a case, the synchronization mode cannot be switched from the internal synchronization mode to the external synchronization mode.